Complementary metal oxide semiconductor (CMOS) technologies have traditionally employed a gate dielectric, usually a silicon dioxide layer called a "gate oxide" layer, of a single thickness in forming all the CMOS transistors on a substrate. To meet the demand for increased transistor switching speeds, the gate oxide thickness has been decreased, while gate oxide processing techniques have been improved and power supply voltages have been lowered to maintain acceptable gate oxide reliability.
Current demands for high density and performance require design rules of about 0.25 microns and under in certain devices such as microprocessors, nonvolatile memories and programmable logic circuits. Such high density demands have accelerated reduction in gate oxide thickness (and therefore in power supply voltage) to a greater extent than in other semiconductor devices with which they may be associated; e.g., other devices on a personal computer motherboard. However, some transistors formed on the same substrate as microprocessors, memories or programmable logic circuits, such as transistors in input/output (I/O) circuits, must communicate with devices operating at a higher voltage and, therefore, must withstand a higher voltage.
One approach to this problem is to use a dual-cascaded I/O circuit design to spread the higher I/O voltage across two transistors, thereby providing adequate gate oxide reliability even with the thin gate oxide of the microprocessor, memory or programmable logic circuits. Unfortunately, as feature sizes of microprocessors, etc. shrink to 0.18 .mu.m and below, the correspondingly thinner gate oxide of these devices (e.g. less than 30 .ANG.) and their lower operating voltage (e.g. 1.5 volts) are incompatible with the I/O voltage (e.g. 3.3 volts) of other, higher voltage devices, even if a dual-cascade I/O design is employed. It is possible to employ a triple-cascade I/O design, but such a design is disadvantageous because it consumes significant amounts of valuable space on the wafer.
To avoid the limitations of cascaded I/O circuit design, some CMOS devices with extremely fine features (e.g. 0.18 .mu.m or less) utilize a "dual gate oxide" approach, wherein the gate oxide of I/O circuits is thicker than the gate oxide of the remainder of the transistors on the substrate. According to this technique, field isolation areas are formed on the substrate to define active areas, and then transistor channel implants are performed, such as well implants, field implants, punchthrough implants and threshold adjust implants. A first, thick gate oxide is formed, as by thermal oxidation, over the active areas to a thickness of, e.g., about 50 .ANG., then the thick gate oxide is masked and etched to remove it from the portions of the active areas that are to have a thinner gate oxide. A second, thinner gate oxide is then formed, as by thermal oxidation, on the active areas to a thickness of, e.g., about 30 .ANG., resulting in transistors having two different thicknesses of gate oxide on the same wafer.
Devices with small feature sizes, such as 0.18 .mu.m or less, require sharply defined dopant profiles in their channel regions to optimize transistor speed and short-channel effects. To maintain these sharply defined profiles, temperature cycles must be minimized after the transistor channel dopants are implanted. Disadvantageously, the extra gate oxidation step in the dual gate oxide process flow described above diffuses the previously implanted channel dopants to such an extent that the channel doping profile is disturbed, thereby adversely affecting the electrical characteristics of the finished device.
There exists a need for a method of manufacturing a semiconductor device having transistors with differential gate oxide thicknesses wherein the channel doping profile is not adversely affected, particularly in semiconductor devices having a design rule of less than about 0.18 .mu.m.